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MESI protocol
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31	The SGI Origin: A ccNUMA Highly Scalable Server James Laudon and Daniel Lenoski Silicon Graphics, IncNorth Shoreline Boulevard Mountain View, California 94043 Add to Reading List Source URL: www.sgidepot.co.uk Language: English - Date: 2008-04-15 16:23:23 Computer architecture Computer memory Parallel computing SGI Origin Non-Uniform Memory Access R10000 CPU cache Cell MESI protocol Computing Cache coherency Computer hardware
32	UMA System Performance Analysis A project executed in partial fulllment for the requirements of Computer Systems Performance Analysis Teacher: Prof. T. Stricker Assisted by: Dipl.-Inf. Chr. Kurmann Add to Reading List Source URL: www.cs.inf.ethz.ch Language: English - Date: 2000-03-09 12:12:40 Computer memory CPU cache Central processing unit MESI protocol Parallel computing Fast Fourier transform Cache algorithms Cache-oblivious algorithm Cache Computer hardware Computing
33	A Framework for Using Processor Cache as RAM (CAR) Eswaramoorthi Nallusamy University of New Mexico October 10, 2005 Add to Reading List Source URL: coreboot.org Language: English - Date: 2007-04-03 20:28:37 Computer memory Cache CPU cache Central processing unit MESI protocol Memory type range register Cache algorithms MSI protocol Cache coherency Computing Computer hardware
34	Implementation tradeoffs in the design of flexible transactional memory support Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2010-12-08 11:53:44 Information Data management Computer memory Cache coherency Concurrency control CPU cache Cache Transactional memory MESI protocol Transaction processing Computing Data
35	Flexible Decoupled Transactional Memory Support∗ Arrvindh Shriraman Sandhya Dwarkadas Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2008-01-16 21:04:48 Data management Computer memory Computing Concurrency control Databases CPU cache Transactional memory Schedule MESI protocol Transaction processing Data Information
36	Introduction to AMBA® 4 ACE™ and big.LITTLE™ Processing Technology Ashley Stevens Add to Reading List Source URL: www.arm.com Language: English - Date: 2013-10-31 06:19:27 Computer architecture MESI protocol MOESI protocol Cache ARM Cortex-A15 MPCore Advanced Microcontroller Bus Architecture Dragon protocol MSI protocol Cache coherency Computing Computer hardware
37	Hardware Acceleration of Software Transactional Memory ∗ Arrvindh Shriraman Virendra J. Marathe Sandhya Dwarkadas Michael L. Scott David Eisenstat Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2006-05-18 20:56:53 Data Concurrency control Computer memory Cache coherency Software transactional memory Transactional memory MESI protocol Schedule Linearizability Transaction processing Computing Data management
38	ASPLOS[removed]Architecture Support for Data Isolation & Memory Monitoring Arrvindh Shriraman, Sandhya Dwarkadas, and Michael L. Scott Department of Computer Science, University of Rochester Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-04-01 17:28:51 Computer hardware Concurrent computing Concurrency control Transaction processing Central processing unit CPU cache Cache Transactional memory MESI protocol Computing Computer memory Cache coherency
39	An Integrated Hardware-Software Approach to Flexible Transactional Memory∗ Arrvindh Shriraman Hemayet Hossain Sandhya Dwarkadas Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2007-01-31 16:34:34 Information Concurrency control Databases Computer memory Serializability Transactional memory MESI protocol Linearizability Nested transaction Transaction processing Data management Data
40	Allocation Policy Analysis for Cache Coherence Protocols for STT-MRAM-based caches A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA Add to Reading List Source URL: conservancy.umn.edu Language: English - Date: 2014-12-31 03:01:17 Cache coherency Non-volatile memory Magnetoresistive random access memory Spintronics CPU cache MESI protocol Random-access memory Cache coherence Nonvolatile BIOS memory Computer hardware Computing Computer memory